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Lattice Semiconductor
Turbo Decoder User’s Guide
Additional Signals for External Memory
When external memory is used with this core additional signals are provided to form the interface to the external
memory. These are detailed below.
3GPP
In the case where external memory is selected, the I/O pins in Table 3 will be added to the block for exchanging
data with the memory in the case of 3GPP. It is assumed that data and parity are stored in different memory buff-
ers. Non-interleaved and interleaved parity are stored in different buffers.
Table 3. Additional I/Os Due to External Memory for 3GPP
Port Name
g1_dat_buf1
g2_dat_buf1
g1_par_odd1
g2_par_odd1
g1_par_even1
g2_par_even1
data_to_mem
data_waddr
wren_dat_buf1
wren_par1_buf1
wren_par2_buf1
g1_rden
g2_rden
g1_dat_raddr
g2_dat_raddr
g1_par_raddr
g2_par_raddr
I/O Type
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Width
3-6
3-6
3-6
3-6
3-6
3-6
3-6
3-6
1
1
1
1
1
11-15
11-15
11-15
11-15
Signal Description
Information data port 1
Information data port 2
Parity 1 (systematic) data port 1
Parity 1 (systematic) data port 2
Parity 2 (interleaved) data port 1
Parity 2 (interleaved) data port 2
Information/parity data to memory
Information/parity Write address
Write enable for Information data
Write enable for parity 1 (systematic)
Write enable for parity 2 (interleaved)
Information/parity read enable port 1
Information/parity read enable port 2
Information read address port 1
Information read address port 2
Parity read address port 1
Parity read address port 2
In the case where double buffering is selected along with the external memory the I/O pins in Table 4 will also be
added to the core for exchanging data with the second buffer in the case of 3GPP.
Table 4. Additional I/Os Due to Double Buffering for 3GPP
Port Name
g1_dat_buf2
g2_dat_buf2
g1_par_odd2
g2_par_odd2
g1_par_even2
g2_par_even2
wren_dat_buf2
wren_par1_buf2
wren_par2_buf2
I/O Type
Input
Input
Input
Input
Input
Input
Output
Output
Output
Width
3-6
3-6
3-6
3-6
3-6
3-6
1
1
1
Signal Description
Information data port 1
Information data port 2
Parity 1 (systematic) data port 1
Parity 1 (systematic) data port 2
Parity 2 (interleaved) data port 1
Parity 2 (interleaved) data port 2
Write enable for Information data
Write enable for parity 1 (systematic)
Write enable for parity 2 (interleaved)
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